d a t a sh eet product speci?cation file under integrated circuits, ic06 december 1990 integrated circuits 74hc/hct563 octal d-type transparent latch; 3-state; inverting for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications the ic06 74hc/hct/hcu/hcmos logic package information the ic06 74hc/hct/hcu/hcmos logic package outlines
december 1990 2 philips semiconductors product speci?cation octal d-type transparent latch; 3-state; inverting 74hc/hct563 features 3-state inverting outputs for bus oriented applications inputs and outputs on opposite sides of package allowing easy interface with microprocessor common 3-state output enable input output capability: bus driver i cc category: msi general description the 74hc/hct563 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74hc/hct563 are octal d-type transparent latches featuring separate d-type inputs for each latch and inverting 3-state outputs for bus oriented applications. a latch enable (le) input and an output enable ( oe) input are common to all latches. the 563 is functionally identical to the 573, but has inverted outputs. the 563 consists of eight d-type transparent latches with 3-state inverting outputs. the le and oe are common to all latches. when le is high, data at the d n inputs enter the latches. in this condition the latches are transparent, i.e. a latch output will change state each time its corresponding d-input changes. when le is low the latches store the information that was present at the d-inputs a set-up time preceding the high-to-low transition of le. when oe is low, the contents of the 8 latches are available at the outputs. when oe is high, the outputs go to the high impedance off-state. operation of the oe input does not affect the state of the latches. quick reference data gnd = 0 v; t amb =25 c; t r =t f = 6 ns notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): p d =c pd v cc 2 f i + ? (c l v cc 2 f o ) where: f i = input frequency in mhz f o = output frequency in mhz ? (c l v cc 2 f o ) = sum of outputs c l = output load capacitance in pf v cc = supply voltage in v 2. for hc the condition is v i = gnd to v cc for hct the condition is v i = gnd to v cc - 1.5 v ordering information see 74hc/hct/hcu/hcmos logic package information . symbol parameter conditions typical unit hc hct t phl/ t plh propagation delay d n , le to q n c l = 15 pf; v cc =5 v 14 16 ns c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per latch notes 1 and 2 19 19 pf
december 1990 3 philips semiconductors product speci?cation octal d-type transparent latch; 3-state; inverting 74hc/hct563 pin description pin no. symbol name and function 2, 3, 4, 5, 6, 7, 8, 9 d 0 to d 7 data inputs 11 le latch enable input (active high) 1 oe 3-state output enable input (active low) 10 gnd ground (0 v) 19, 18, 17, 16, 15, 14, 13, 12 q 0 to q 7 3-state latch outputs 20 v cc positive supply voltage fig.1 pin configuration. fig.2 logic symbol. fig.3 iec logic symbol.
december 1990 4 philips semiconductors product speci?cation octal d-type transparent latch; 3-state; inverting 74hc/hct563 fig.4 functional diagram. function table notes 1. h = high voltage level h = high voltage level one set-up time prior to the high-to-low le transition l = low voltage level l = low voltage level one set-up time prior to the high-to-low le transition z = high impedance off-state operating modes inputs inter- nal latches out- puts oe le d n q 0 to q 7 enable and read register l l h h l h l h h l latch and read register l l l l l h l h h l latch register and disable outputs h h l l l h l h z z fig.5 logic diagram.
december 1990 5 philips semiconductors product speci?cation octal d-type transparent latch; 3-state; inverting 74hc/hct563 dc characteristics for 74hc for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: bus driver i cc category: msi ac characteristics for 74hc gnd = 0 v; t r =t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay d n to q n 47 17 14 145 29 25 180 36 31 220 44 38 ns 2.0 4.5 6.0 fig.6 t phl / t plh propagation delay le to q n 47 17 14 145 29 25 180 36 31 220 44 38 ns 2.0 4.5 6.0 fig.7 t pzh / t pzl 3-state output enable time oe to q n 47 17 14 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 fig.8 t phz / t plz 3-state output disable time oe to q n 50 18 14 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 fig.8 t thl / t tlh output transition time 14 5 4 60 12 10 75 15 13 90 18 15 ns 2.0 4.5 6.0 fig.6 t w enable pulse width high 80 16 14 14 5 4 100 20 17 120 24 20 ns 2.0 4.5 6.0 fig.7 t su set-up time d n to le 50 10 9 11 4 3 65 13 11 75 15 13 ns 2.0 4.5 6.0 fig.9 t h hold time d n to le 4 4 4 - 6 - 2 - 2 4 4 4 4 4 4 ns 2.0 4.5 6.0 fig.9
december 1990 6 philips semiconductors product speci?cation octal d-type transparent latch; 3-state; inverting 74hc/hct563 dc characteristics for 74hct for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: bus driver i cc category: msi note to hct types the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given in the family specifications. to determine d i cc per input, multiply this value by the unit load coefficient shown in the table below. ac characteristics for 74hct gnd = 0 v; t r =t f = 6 ns; c l = 50 pf input unit load coefficient d n le oe 0.35 0.65 1.25 symbol parameter t amb ( c) unit test conditions 74hct v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay d n to q n 18 30 38 45 ns 4.5 fig.6 t phl / t plh propagation delay le to q n 19 35 44 53 ns 4.5 fig.7 t pzh / t pzl 3-state output enable time oe to q n 20 35 44 53 ns 4.5 fig.8 t phz / t plz 3-state output disable time oe to q n 22 35 44 53 ns 4.5 fig.8 t thl / t tlh output transition time 5 12 15 18 ns 4.5 fig.6 t w enable pulse width high 16 5 20 24 ns 4.5 fig.7 t su set-up time d n to le 10 3 13 15 ns 4.5 fig.9 t h hold time d n to le 5 - 1 5 5 ns 4.5 fig.9
december 1990 7 philips semiconductors product speci?cation octal d-type transparent latch; 3-state; inverting 74hc/hct563 ac waveforms fig.6 waveforms showing the data input (d n ) to output ( q n ) propagation delays and the output transition times. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. fig.7 waveforms showing the latch enable input (le) pulse width, the latch enable input to output ( q n ) propagation delays and the output transition times. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. fig.8 waveforms showing the 3-state enable and disable times. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. package outlines see 74hc/hct/hcu/hcmos logic package outlines . fig.9 waveforms showing the data set-up and hold times for d n input to le input the shaded areas indicate when the input is permitted to change for predictable output performance. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v.
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